Summary of the Linux kernel is designed to take into account a variety of microprocessors on implementation, have taken into account in the 64-bit microprocessors (such as Alpha) on the implementation of four, memory management, 1, the basic framework of the Linux kernel is designed to take into account a variety of microprocessors on implementation, have taken into account in the 64-bit microprocessors (such as Alpha) implementation, not only for i386 architecture to design its mapping mechanism, but to just mock, virtual microprocessors and MMU (memory management unit) as the basis for designing a common pattern, then treat it separately to concrete microprocessor.
Thus, the Linux kernel mapping mechanism is designed into three layers, in the page directory and page table created a layer of "intermediate directories". In code, page directory called PGD, the intermediate directory called PMD and page table called PT. The table entries are called PT PTE. PGD, PMD, PT is an array, appropriate, and logically also linear address from high to low is divided into 4 members section, an area several, as the directory index of PGD, the intermediate directory PMD of subscripts, page table of subscript and displacement of the physical page. On the i386 processor, the CPU is actually not by three layers but by a two-tier model to address mapping, which will need to use a virtual three-tier mapping to concrete two layers of mapping, skipping the intermediate of PMD levels. 2. address mapping of the entire process will be on i386 microprocessors in the address you type mapping, and then to make a page style mapping. While the Linux approach actually make-mapping process does nothing for me. Following a simple procedure to see Linux under address mapping of the whole process: the # include greeting () {printf ("Helloworld! ”); } main() { greeing(); The procedures in the master} function call greeting to display "Helloworld!" , Compiled and disassembly, we received the results of its disassembly. 08048568: 8048568: 55push1% ebp 8048856b: 89e5mov1% esp,% ebp 804856b: 6804940408push1 $ 0x8048404 8048570: e8fffeffffcall8048474 8048575: 83c404add1 $ 0x4,% esp 8048578: c9leave 8048579: c3ret 804857a: 89f6mov1% esi,% esi 0804857c: 804857c: 55push1% ebp 804857d: 89e5mov1% esp,% ebp 804857f: e8e4ffffffcall8048568 8048584: c9leave 8048585: c3ret 8048586: 90nop 8048587: 90nop as can be seen from above, greeting () address to 0x8048568. In elf format executable code, always start Scheduler 0x8000000 "snippet", on each program. When the program is executed in the main to the "call8048568" this instruction that you want to transfer to a virtual address 8048568. First, type mapping phase. Address 8048568 is a program of the portal and, more importantly, in the implementation process have CPU's EIP points to, so in the code snippet. I386cpu use CS's current value as a selection of maps. Kernel in the establishment of a process is to set its segment registers, DS, ES, SS are set into the CS _USER_DS, set to _USER_CS, that is to say, in the Linux kernel stack segment and code snippets are not. IndexTIDPL # define_KERNEL_CS0x100000000000010 | 0 | 00 # define_KERNEL_DS0x180000000000011 | 0 | 00 # define_USER_CS0x230000000000100 | 0 | 11 # define_USER_DS0x2B0000000000101 | 0 | 11 _KERNEL_CS: index = 2, TI = 0, DPL = 0 _KERNEL_DS: index = 3, TI = 0, DPL = 0 _USERL_CS: index = 4, TI = 0, DPL = 3 _USERL_DS: index = 5, TI = 0, DPL = 3 TI are all 0, use the global Description table. The kernel of DPL is 0, the highest level; user of DPL is 3, the minimum level. _USER_CS GDT is the table in item 4, the code initializes the GDT content as follows: ENTRY (gdt-table) .quad0x0000000000000000/* .quad0x0000000000000000 NULLdescriptor *//* notused */.quad0x00cf9a00000ffff/* .quad0x00cf920000 0x10kernel4GBcodeat0x00000000 */0ffff/* .quad0x00cffa00000ffff 0x18kernel4GBdataat0x00000000 *//* 0x23user4GBcodeat0x00000000 */.quad0x00cff200000ffff/* 0x2buser4GBdataat0x00000000 */GDT table first, second, and third to fifth total four corresponds to the previous four segment register values. The four items of content description: K_CS: 00000000110011111001101000000000 00000000000000001111111111111111 K_DS: 00000000110011111001001000000000 00000000000000001111111111111111 U_CS: 000000001100111111111101000000000 00000000000000001111111111111111 U_DS: 00000000110011111111001000000000 00000000000000001111111111111111 these four description of the following content is the same. · BO-B15/B16-B31 0 base address full-0 · LO-L15, L16-L19 are 1 segment boundaries are 0xfff · G-bit is 1 long are 4 · D-bit are 132-bit instruction · P bit is 1 four segments in memory is the permission levels for different, kernel, user level 0 to level 3. So, each segment is from address 0 start to the entire virtual memory space 4GB, virtual address to a linear address mapping to maintain the original value unchanged. Back to greeting program through-map the address 8048568 mapped to itself, be a linear address. Each process has its own page directory each time a scheduled a PGD, the process to enter is running, the kernel will have to be running process set up control register CR3, MMU hardware is always obtained from the CR3 of current processes in the page directory pointer. When a program wants to go to address 0x8048568, processes are running, CR3 is already set up to point to this process in the page catalog. 8048568: 00001000000001001000010101101000 follow the linear address format, maximum 10 0000100000, decimal 32, 32 on the following scale to the page catalog table to find the page directory entries. This page directory entries of 20 bits followed on 12 0 to get a pointer to the page table. Find the page table, and then look at the middle of the linear address 10 bit 001001000, 72 in decimal. The 72-subscript in the found page table to find the corresponding table entries. Page table entries to high 20-bit added after 12 0 got physical memory base address of the page. Linear 12-bit address of the base and the base address of the physical page is added to access physical address. 3 address mapping efficiency analysis in page-mapping process, the CPU to access memory, three times, first page directory, the second is page table, the third is the real target you want to access. In this way, the original without paging mechanism once the memory can be accessed, changed three times the memory can be accessed, the obvious implementation of pagination in efficiency is too large for the sacrifice. In order to reduce this overhead, has recently been performed by address translation results will be retained in the MMU conversion fallback buffer (TLB). Although at the first available to specific page contents and page table to read into memory, but once you have mounted the TLB, you do not need to go read up in memory, and all these are done by the hardware, so quickly. TLB corresponding permissions greater than 0 level that is not visible, only at the system level 0 of the program to manipulate it. When the contents of the CR3 changes, all of the contents of TLB will be automatically become invalid. Linux in _flush_tlb macros is the use of this work. _Flush_tlb just two compilation instructions, the CR3 value stored in the temporary variable tmpreg and immediately tmpreg values are copied back to the CR3, so will the entire contents of TLB to is not valid. In addition to the invalid all the contents of TLB, have selected an invalid tlb a record, it will use to INVLPG instruction. 5. process management 1.I386 hardware tasks switching mechanism in the Intel i386 architecture design takes into account the processes of management and scheduling, and hardware support to switch between tasks. To this end, Intel in i386 system structure created a new section "task state segment" TSS. A TSS although like code snippets, segments, etc., is also a paragraph, it is a 104 bytes of data structure, used to record a task critical state information. Like other segments, the TSS to description table has a table entry. Although TSS can only GDT, but should not be placed in any LDT in or IDT. To select an item from one section to access a TSS, and select the item in TI-bit is 1, will result in a GP exception. In addition, the CPU is also an additional task register TR, a pointer to the current tasks of the TSS. Accordingly, it has added one instruction LTR, TR-register for mount operation. Like CS and DS, TR also have a program that is not visible, choose a section whenever the code loaded into TR, the CPU would be self--Find the TSS description entry and loaded into the program invisible TR to accelerate later access TSS segment. Also, in the IDT tables, in addition to interrupt the trap door, door and call door that also defines a task. Task door contains one paragraph selected codes. TSS When the CPU was interrupted while passing through a door, the task of selecting code in the door automatically mount TR, TR point to the new TSS, and complete the task switching. CPU also can pass JMP and CALL instructions for task switching, when jump or call target segment actually point to one of the GDT table describing the item, the TSS will cause a task switching. 2.Linux task switching and field protection of Intel design on task switching is very comprehensive, but provides a very simple task switching mechanism. However, Linux does not use i386 hardware supplied task switching mechanism. Linux is doing, is to a great extent from the efficiency point of view. There is a CPU automated this task switching is not only the equivalent of one instruction. In fact, JMP instruction in through the i386 or CALL instructions to complete the task switching process is a fairly complex process, its implementation process up to 300 CPU clock cycle. In the implementation process, the CPU is actually done all you need to do, but some of it under certain conditions
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