6 apply to embedded system programmable chip embedded system hardware volume, weight, power consumption, cost, reliability, have different levels of requirements, some indicators will have special requirements.
For example, mobile phone type of mobile device on power consumption particularly sensitive, information appliances for cost sensitive, and military equipment on reliability index requires extremely high. Therefore, the different application areas, the focus of their needs are different, we need to give serious consideration to choose the right hardware platform. IC has entered a submicron, even very large scale integration of nano-era, with system-level programmable chips embedded system hardware, regardless of size, weight, power consumption, cost, reliability, and so you can achieve the desired result will be the best option. Therefore, specific chip design is an embedded system design of one of the core technology. Applies to the chip for embedded systems can be divided into General and specific chip two categories are discussed as follows: 6.1 universal chip chips mainly standard cell IC, FPGA and gate arrays, etc. Now compare: IC 6.1.1 standard units (that is, half a custom ASIC chip) · advantages: optimal space utilization · can · get the best!. · shortcomings: the establishment of a solid design · Foundation development resources investment. Design difficult ·, request design tools features strong, design with technology continually upgrading; in the design rules length is less than 0.25 μm deep sub-micron (DSM) design, designers typically takes a lot of effort to resolve DSM effect, such as migration, antenna effect. The problem is mainly composed of very small physical structure. This is in the back-end design processes used for the development of tools to address these effects cause. · design staff professional knowledge has set higher requirements, while also need some professional design company provides tools to use. The developer tools area of expertise, the more likely they are to obtain optimal design (smallest at best performance). Design for existing · and tools apply two challenges, shorten design times naturally become project scheduling a determining factor. · prospective unit IC related non-recurring design cost (NRENon-recurringEngineering) costs. The fee is predominantly for etching mask, mask design rule length in MCU μ m following the NRE cost typically up to thousands of dollars, in this case to maintain the balance of payments requires that the chip has enough sales. 6.1.2FPGA (field-programmable gate array) ·: · PGA-costly. · standard cell IC and gate array, the advantages of having programmable FPGA, mask costs; chip completes can be modified through programming, hardware risks. ·: (as technology advances, some shortcomings are gradually overcome) when doing mass production, the FPGA has cost advantages will weaken. · PGA programmability of Silicon area, and thus require larger higher power consumption. In order to adapt to the increased external pin, package prices are more expensive. Even the small batch production, mask-programmable ASIC programme costs can sometimes lower number. 6.1.3 gate array · advantages: · for door structure complete chip, such as "door sea" structure, the design engineer only need to do is through the metal layer of ASIC gate level routing implementation. · gate array technology can achieve the system frequency exceeding current FPGA technology can provide frequency. · gate array development work is relatively easy, as most of you can auto-complete. Gate array development costs much less than the standard unit of IC, because the circuit is only necessary to increase the metal layer, greatly reducing the design steps. · bad: compared with the standard unit of IC, gate array's main drawback is that the area utilization and performance are relatively low. standard cell · IC (i.e. semi-custom ASIC chip) · advantages: optimal area utilization. Get the best performance. · bad: to establish a solid basis for the design, development and resource investment.
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