8.4 design reuse related organizations due to IP has become the chip design of an important element, so the industry established a different organization in order to promote the development of the design reuse standards.
Their goal is to develop a set of industry standards, promote the use of IP and to simplify the external IP and the interface between the internal design. The following describes those committed to standards development organizations and their roles. · VSIA Association in September 1996 the virtual interface Alliance (VSIA) was established, the Union was set up in order to promote more than one source IP cores between "mix and match" and develop open standards, thereby accelerating the SoC development. The Union members from the industry's various systems, semiconductor companies, IP and EDA company. VSIA hope by publishing an open interface standard for creating an environment that VC (virtual device-VirtualComponent) will be able to at least (or no) glue logic easily meet based on function and physical level of demand for the "virtual interface". VSIA standards include the industry's existing standards, open or proprietary data format, the goal is to create a deliverable kernel standard format. This kernel is completely independent of the individual user's unique design processes · OpenMORESynopsys company and! MentorGraphics group company to carry out the famous OpenMORE (OpenMeasureofReuseExcellence) program, which is built on the two companies jointly launched "the reuse methods Guide" (RMM) on the basis of an evaluation plan. OpenMORE IP kernel design is defined as can be seen as a complete SoC design part of independent design. In addition, RMM also defines macros for soft soft core (softmacro) or to deliver integrated RTL code; instead, the kernel is defined as a hard core of hard macro or to GDSII file form delivered by the kernel. Hard core can be a complete design, layout and wiring. When designers decided to purchase for their design IP core, the IP evaluation will become an important part of the design process. OpenMORE programme is expected to pass to the kernel multiplexing quality provide reasonable assessment model and simplifies IP assessment process. IP developers in a worksheet to fill in for hard core and soft core rules description and application guide, users use this procedure to get the final score to evaluate kernel design methods. Sheet assessment aimed at improving the core reusability, thereby improving IP core integration to final SoC design speeds and predictability. Note that in each company independently developed IP design standards, they often do not guarantee the desired kernel with actual kernel function match exactly, because there is no guarantee that other companies also have those who can purchase a third-party IP and design their own IP companies the same design reuse style. Most users are those that usually OpenMORE using in-house development of kernel and third-party IP company. IP providers can adopt OpenMORE to make it easier for users to use the kernel, thus reducing the required customer support RAPID and VCX ·. Organization of development and marketing of IP company in 1996 set up a reusable specific applications of intellectual property rights and Development Association (RAPID). The Association is committed to promoting the use and acceptance of external IP products. The goal is through the establishment of related guidelines, encouraged the members of the Association or within the electronics industry and industry standards organizations to use good business and design practices that enable designers to more easily use IP. "Virtual device Exchange" (VCX) of the Organization's mission is to create an efficient, open international market framework to promote virtual devices (VC) service. They set up a "trading center", stock and commodity markets best characteristics, services and structures for VC deal. Both organizations set up joint venture to accelerate development and VCX IP Commerce schema in the world. 8.5 industry IP core ideas in the past few years, the industry and research institutions for IP in the design process of some discussion, they both from the theoretical and practical aspects discussed IP for SoC design. Although the market has emerged very early on, but the kernel IP core market position yet established, therefore in the mature market development process, the core product of the user and the supplier still faces a severe test. · user's opinions in kernel design developers has been the lack of infrastructure. Use of third-party kernel, the biggest problem lies in the documentation. Documentation, you also need to be able to provide 100% coverage of the test platform, to verify that the kernel design. Purchase IP core designer not only need RTL files, you also need to protect the design performance. Because IP product licenses and design integration process, especially when the design using multiple vendors in the kernel, the difficulty increases allows integration with third-party IP if questionable. These problems usually deferred product time to market, further offset design uses external IP. In the design process in strict compliance with the norms of corporate IP is usually needed to spend considerable resources to develop internal IP policies and requirements. Not only internally developed IP design methods to be followed, but before you purchase your external IP requires careful assessment of the kernel. Comparative evaluation of IP, the average sustained long for several weeks or even months. The cost of assessing IP is quite amazing, this is not conducive to the IP into the small business development process. · vendor point of view IP user first from IP vendor kernel gets experience is very important. Since the IP industry still growing in relative terms, IP reputation among the engineers is critical. In fact, some IP vendors even claims that 80% of sales is "withhighpraise" results. Clearly, and customer relationships is essential. But IP industry began to seek the help of the Internet, the vendor will not only show the products via the Internet, but also as a mode of delivery. Programmable logic devices company in IP development put a lot of manpower and material resources. Like the Altera and Xilinx these companies have been successful IP productsDevelopment as a hundred new devices products for door grade success factors. These companies have developed IP design technology, and through third-party IP vendors to help customers understand the new design methods and provides the user with kernel program. The two companies also develop your own kernel, and design tools. Although these companies also sell IP cores, but their goal is to shorten the time for FPGA design in order to sell more Silicon. You can leave through the sale of the kernel, in a year will be the kernel node-locked (node-locked). Allow users in this one year period of its use at any time and in the design of the kernel. Some silicon vendors allow specific design using the kernel, but in other design charge a minimal kernel reuse fees. While other silicon vendors to reuse the kernel entirely without any restrictions. Sale of IP to their main business of third-party IP vendors can choose different sales strategy. They can sell the kernel to receive related fees, users can set the kernel to use for a specific design or future any design, or you can select the pieces billing purchases kernel, thereby reducing the risk of the user to purchase the kernel. In addition, you can take the above two patterns in mixed mode.
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