On Arm Linux interrupt Vector vector table creation process

Linux memory management with the mmu, arm of interrupt what? and we interrupts on bare Board has no difference? let us start from the source code, do a rough analysis: init/main.c-> start_kernel ()->//-----------------------------------------------1.trap_init trap_init () () function is located in//gliethttp arch/arm/kernel/traps.cvoid__inittrap_init (void) {externvoid__trap_init (unsignedlong); unsignedlongbase = vectors_base ();//returns base address 0xfff0000__trap_init interrupted base (base);//the base to the base address, initialization vector interrupt vector table if (base! = 0) printk (KERN_DEBUG "Relocatingmachinevectorsto0x% 08lx\n", base); # ifdefCONFIG_CPU_32modify_domain (DOMAIN_USER, DOMAIN_CLIENT); # endi}//gliethttpinclude/arch/asm-arm/proc-armv/system.externunsignedlongcr_alignment//--------------------------------------2.vectors_base (); # if__LINUX_ARM_ARCH__ > = 4//at91rm9200 is armV4 structure # definevectors_base () ((cr_alignment & CR_V)? 0xffff0000: 0) # else # definevectors_base () (0) # endi can see ARMv4 following version, the address is fixed to 0; ARMv4 and above versions, arm and the address of the interrupt vector table by CP15 c1 coprocessor register V bits (bit [13]) control, v, and the interrupt vector table of correspondence between the following: V = 0 ~ 0x00000000 ~ 0x0000001CV = 1 ~ 0xffff0000 ~ 0xfff001C//------------------------------------------2.1cr_alignment//gliethttparch/arm/kernel/entry-armv.SENTRY (stext) movr12, r0movr0, # F_BIT | I_BIT | MODE_SVC  @ makesuresvcmodemsrcpsr_c, r0  @ andallirqsdisabled//__lookup_processor_type query processor type, [glietttp up later <浅析head-armv.s>] returns the value//2007-07-04//r9 = processorID//read the c0 cp15 registers//r10 = pointertoprocessorstructure//the following will addpc, r10, # 12, jump to __arm920_setup//gliethttp in vmlinux-armv.lds.in//__proc_info_begin =.;/

/*(.proc.ino)//__proc_info_end=.;/ /See 2.2bl__lookup_processor_typeteqr10, # 0 & nbsp @ invalidprocessor? moveqr0, # ' yes, error'p'beq__errorbl__lookup_architecture_typeteqr7 p'  @, #, 0, & nbsp @ invalidarchitecture? moveqr0, # ' a'  @ yes, error'a'beq__error//create temporary __create_page_tables arm start using front page table bl__create_page_tablesadrlr 4M, __ret  @ returnaddressaddpc, r10, # 12 & nbsp @ initialiseprocessor.type__switch_data,% object__switch_data: .long__mmap_switced.longSYMBOL_NAME (__bss_start) .longSYMBOL_NAME (_end) .longSYMBOL_NAME (processor_id) .longSYMBOL_NAME (__machine_arch_type) .longSYMBOL_NAME (cr_alignment) .longSYMBOL_NAME (init_task_union) + 8192/** EnabletheMMU.Thiscompletelychangesthestructureofthevisible * Ifyouhaveanenquiryaboutthis memoryspace.Youwillnotbeabletotraceexecutionthroughtis. *, * please * checkthelinux-arm-kernel * mailinglistarchivesBEFOREsendinganotherposttothelist. */.type__ret,% function__ret: ldrlr, __switc_datamcrp15, 0, c0, c1, r0//put __arm920_setup value set r0, place the cp15 c1 coprocessor register mrcp15, 0, c0, c1, r0, 0 & nbsp @ readitback.movr0, r0//fill the armv4-line: movr0, r0 corresponds to a nop, so the corresponding 2 nop and a movpc, lr just three "useless" operation movr0, r0movpc, lr//jump to __mmap_switched function gliettttp/** ThefollowingfragmentofcodeisexecutedwiththeMMUon, anduses * absoluteaddresses; thisisnotpositionindependent. ** r0 = processorcontrolregister * r1 = machineID * r9 = processorID */.align5__mmap_switced: adrr3, __switch_data + 4ldmiar3, {r4, r5, r6, r7, r8, sp @ r2 = compat//2007-07-04glietttp//r4-r5 ~ __bss_start//_end//r6-r7-processor_id//__machine_arc_type//r8 ~ cr_alignment//sp ~ (init_task_union) + 8192//the following step, the processor_id, __machine_arch_type cr_alignment assignment glietttpmovfp, # 0 & nbsp @ ClearBSS (andzerop) 1: cmpr4, r5//bss area Ching 0strccfp, [r4], # 4bcc1bstrr9, [r6] & nbsp @ SaveprocessorIDstrr1, [r7] & nbsp @ Savemachinetype # ifdefCONFIG_ALIGNMENT_TRAPorrr0, r0, # 2 & nbsp @ ...........A. # endibicr2, r0, # 2 & nbsp @ Clear'A'bit//r2 storage disable TRAP queue failure after r0 value//r8-> cr_alignment, stmiar8 cr_no_alignment//so, {r0, r2}, cr_alignment = r0, cr_no_alignment = r2stmiar8, {r0, r2} & nbsp @ SavecontrolregistervaluesbSYMBOL_NAME (start_kernel)//enter the kernel C program//--------------------------------------2.2__arm920_proc_ino//gliethttparch/arm/mm/proc-arm920.S.section ".proc.info alloc", #, #, # execinstr.type__arm920_proc_info object__arm920_proc_ino://the address stored in the r10 .long0x41009200.long0xff00f0.long0x00000c1e  @ mmulagsb__arm920_setup//addpc, r10, # 12gliethttp will keep the CPU execution b__arm920_setup jump instruction .longcpu_arc_name.longcpu_elf_name.longHWCAP_SWP | HWCAP_HALF | HWCAP_TUMB.longcpu_arm920_ino.longarm920_processor_functions.size__arm920_proc_info, .-__arm920_proc_ino//----------------------------------------2.3__arm920_setup.section ".text.init", # alloc, # execinstr__arm920_setup: movr0, # 0mcrp15, 0, r0, c7, c7  @ invalidateI, Dcachesonv4mCrp15, 0, r0, c7, c10, 4 & nbsp @ drainwritebufferonv4mcrp15, 0, r0, c8, c7  @ invalidateI, DTLBsonv4mcrp15, 0, r4, c2, c0  @ loadpagetablepointermovr0, # 0x1f  @ Domains0, 1 = clientmcrp15, 0, r0, c3, c0  @ loaddomainaccessregistermrcp15, 0, r0, c1, c0  @ getcontrolregisterv4/** Clearout'unwanted'bits (thenputtheminifweneedtem) *///gliethttpr0 unit coprocessor cp15 storing a c1 register values, the following code to the value for processing & nbsp @ VIZFRSBLDPWCAMbicr0, r0, # 0x0e00//Ching 0bit [9 ..11] bicr0, r0, # 0x0002//Ching 0bit [1] bicr0, r0, # 0x000cbicr0, r0, # 0x1000  @ ...0000.....000./** Turnonwhatwewant */orrr0, r0, # 0x0031//bit0 = 1 enabling mmuorrr0, r0, # 0x2100  @ .. 1 ....1..11...1//bit13 = 1 interrupt vector table base address for 0xFFF0000 # ifndefCONFIG_CPU_DCACHE_DISABLEorrr0, r0, # 0x0004  @ .............1 .. # endi # ifndefCONFIG_CPU_ICACHE_DISABLEorrr0, r0, # 0x1000  @ ...1 ... ... ... ... # endimovpc, lr